1. Field of the invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device including a bipolar transistor having a reduced parasitic capacitance, and a method for manufacturing such a semiconductor device.
2. Description of related art
In the prior art, as means for realizing a high speed bipolar transistor by reducing a base resistance and a junction capacitance, it has been known to form a graft base in a self-alignment manner by using as a diffusion source a polycrystalline silicon film which forms a base electrode.
For example, a n-type epitaxial layer, which forms a n-type collector region, is formed on an upper surface of a silicon substrate. A field isolation oxide layer is then formed on the n-type epitaxial layer by means of a local oxidation of silicon so as to define a device formation zone. Further, an oxide film is formed on the n-type epitaxial layer within the device formation zone surrounded by the field oxide layer. Thereafter, a p-type polycrystalline silicon layer and an insulating layer are formed in the named order to cover the whole upper surface of the substrate. A first window is formed through the insulating layer situated within the device formation zone, and the p-type polycrystalline silicon layer and the oxide film are etched using as a mask the insulating layer having the first window, so that a second window in alignment with the first window and larger than the first window is formed through the p-type polycrystalline silicon layer and the oxide film. In other words, the edge portion of the insulating layer defining the first window overhangs over the edge of the p-type polycrystalline silicon layer defining the second window.
In this condition, a p-type polycrystalline silicon film is filled into a space formed by the n-type epitaxial layer, an inner wall surface of the second window formed in the oxide film and the p-type polycrystalline silicon layer, and the overhanging edge portion of the insulating layer forming the first window. Then, the substrate is heat-treated to the effect that p-type impurities contained in the p-type polycrystalline silicon film are diffused into the n-type epitaxial layer to form p.sup.+ type graft base region on the upper surface of the n-type epitaxial layer. Thereafter, an insulating film for isolating an emitter electrode and a base electrode from each other is formed on an inner vertical wall of each of the p-type polycrystalline silicon film and the insulating layer and on an upper surface of the insulating layer. Thereafter, p-type impurities are ion-implanted into an exposed area of the n-type epitaxial layer, so as to form a p-type active base region in a surface portion of the n-type epitaxial layer surrounded by the p.sup.+ graft base region. Then, a polycrystalline silicon film is deposited on the exposed area of the epitaxial layer and on the above mentioned insulating film for isolating an emitter electrode and a base electrode from each other, and n-type impurities are ion-implanted so as to bring the deposited polycrystalline silicon film into an n-type and also to form an n-type emitter region in a surface portion of the p-type base region under the deposited polycrystalline silicon film.
In the above mentioned semiconductor device manufacturing process, the graft base region is formed in the self-alignment manner, and therefore, it is possible to a base resistance and a collector junction capacitance. However, since the p-type polycrystalline silicon film used for forming the graft base region in the self-alignment manner is formed beneath the overhanging edge portion of the insulating layer defining the first window, namely at an outside of the contour line defined by the first window formed in the insulating layer, the area of the base region including the graft base region becomes larger than an opening having a minimum dimension which can be formed under a current photolithography technique. Therefore, it has been necessary to ensure a margin between the base region and the field isolation oxide layer, and accordingly, the semiconductor device manufactured in accordance with the above mentioned conventional process could not have a reduced MOS parasitic capacitance between the n-type epitaxial layer forming the collector region and the p-type polycrystalline silicon layer which forms the base electrode.
In addition, the window for forming the graft base region and the emitter region is determined by a photolithographic step which is different from that for defining the field isolation oxide layer, and therefore, the above mentioned margin has to be further enlarged by an extra portion corresponding to an amount of mismatching between the two mask patterns used.